This application claims the priority benefit of Taiwan application Ser. No. 89124859, filed Nov. 23, 2000.
1. Field of Invention
The present invention relates to a clock generator. More particularly, the present invention relates to a stable frequency clock generator without been affected by the variation of driving voltage.
2. Description of Related Art
A charge pump circuit is always designed in a flash memory. A simple ring oscillator generates the clock signal of the charge pump circuit when a single VDD is provided. More particularly, the structure of the ring oscillator illustrated in FIG. 1 and is built with a NAND gate 10 and a number of inverters, for example, inverters 12 and 14. An input node, m, of the NAND gate 10 receives a clock signal, clken, and an output node ,Y, of the NAND gate 10 connects to an input node of the first inverter 12. The output node of the first inverter 12 connects to the input node of the second inverter 14, then the output node thereof directly outputs a new clock signal, clk, or the output node of the second inverter connects to a number of inverters and then output a new clock signal, clk. The output node of the last inverter, for example, say 14 is the last one, also connects to the other input node, n, of the NAND gate 10. This connection allows the new clock signal, clk, return to the NAND gate 10 and with the clock signal, clken, inputs to the NAND gate 10 at the same time and generates a ring-type structure.
However, this structure as mentioned above is only applicable if the variation of VDD is within the range of xc2x110%. If the VDD drops below the range, the clock frequency generated by the ring oscillator will also drop. In general, the clock frequency is inversely proportional to the VDD. For example, if the VDD value drops from 5v down to 3v, the frequency is reduced by 40%. Moreover, because the efficiency of the charge pump circuit is directly proportional to the clock frequency, therefore the efficiency of the charge pump circuit is decreased when the clock frequency is decreasing. Hence, the decreasing range becomes a major problem to maintain a stable output voltage when the charge pump circuit is used as a power source.
The invention provides a stable frequency clock generator that is directly to work out the problem of degraded stability of clock frequency caused by the decrease of VDD.
As embodied and broadly described herein, the invention provides a stable frequency clock generator, which includes a NAND gate, a number of fixed delay units and a number of inverters. More particularly, the NAND gate has a first and a second input nodes and an output node. The first input node receives an input clock signal. Each of the fixed delay units has an input node and an output node. Each inverter has an input node and an output node. Each inverter and the fixed delay unit are connected n series alternately and evenly. The input node of the first fixed delay unit connects to the output node of the NAND gate, and the output of the last inverter connects back to the second input node of the NAND gate for sending a stabilized clock signal as a feedback signal.
More particularly, the input node of the fixed delay unit receives an input signal and the output node sends an output signal. Each fixed delay unit is built with an inverter, a first fixed current source, a first switch controller, a second switch controller, a second fixed current source, a capacitor and a comparator.
In the foregoing description, the input node of the inverter receives an input signal. One node of the first fixed current source connects to a high voltage and the other node of the first fixed current source connects to one node of the first switch controller, which is turned on and off by the input signal. One node of the second switch controller connects to another node of the first switch controller, which is controlled by the output signal of the inverter. The second fixed current source connects the second switch and a low voltage, for example, the ground. One node of the capacitor connects join of the first and the second switch controllers, and the other node connects to the low voltage. The comparator has a first and a second input nodes and an output end. More particularly, the first input node connects to one node of the capacitor and the second input node connects to a fixed voltage source. The output node of the comparator outputs a comparative signal that becomes the output signal of the fixed delay unit.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.